H5GQ2H24AFR-R0C datasheet(61/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

Low Frequency Mode

When Low Frequency Mode is enabled by bit A3, the power consumption of input receivers and clock

trees is reduced. The maximum operating frequency for this low frequency mode is given in the vendor‘s

datasheet.

WCK2CK Auto Synchronization

GDDR5 SGRAMs support a WCK2CK automatic synchronization mode that eliminates the need for

WCK2CK training upon power‐down exit or for reducing WCK2CK training time at low frequency. This

mode is controlled by bit A4. For a detailed description see WCK2CK Auto Synchronization in the section

entitled WCK2CK Training.

DQ(Data) Preamble

When enabled by bit A5, non‐gapless READ bursts will be preceded by a fixed data preamble on the DQ

and DBI# pins of 4 U.I. duration. The programmed READ latency does not change when the Data

Preamble is enabled. The pattern is not encoded with RDBI, however, if RDBI is disabled, the DBI# pins

will not toggle and drive a HIGH.

The on‐chip is enabled by bit A6.

A detailed description of the can be found in the VENDOR ID, TEMP SENSOR and SCAN section.

Half VREFD

This mode allows users to adjust the Vref level in case the GDDR5 SGRAM is operated without

termination: when bit A7 is set to’1’, a Vref level of nominally 0.5 * VDDQ is expected at the VREFD pin or

being generated internally (see Figure 31).

Duty Cycle Correction (DCC)

Bits A10 and A11 control the operation of the duty cycle corrector (DCC). The DCC can be used to cancel

out a static duty cycle error on the WCK clocks. For more details see Duty Cycle Correction (DCC) in the

section entitled OPERATION.

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