H5GQ2H24AFR-R0C datasheet(29/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

Also, this mode works for both normal and PIN mode. When WCK2CK automatic synchronization mode

is enabled, a full WCK2CK training including Phase search is not required after power‐down exit,

although WCK2CK MRS must be issued momentarily for setting the data synchronizers. However, WCK

and CK clocks must meet the tWCK2CKSYNC specification upon power‐down exit. Any allowed command

may be issued after tXPN or after tLK in case the PLL had been enabled upon power‐down entry. The PLL

sequence is not affected by this mode. The use of WCK2CK automatic synchronization mode is restricted

to lower operating frequencies up to fCKAUTOSYNC as described in the datasheets.

Table 12 describes WCK2CK training methods for different frequency ranges. Each Frequency range is

vendor specific. Normal and PIN mode of WCK2CK training are described in Table 12. Each frequency

range is DRAM vendor specific. Divider initialization can be done by training with WCK2CK inversion,

WCK2CK stopping, or WCK2CK auto‐sync. If the user wants to use WCK2CK stop for divider initializa‐

tion instead of WCK2CK auto‐sync, the user must not set the WCK2CK auto‐sync. Low frequency, the

combined use of PIN and WCK2CK auto‐sync modes can minimize WCK2CK training time.

* Note: The divided WCK/WCK# should be aligned CK/CK# by WCK2CK Auto Synchronization or WCK stop mode

The following examples describe the WCK2CK training in more detail.

Example 1: outline of a basic WCK2CK training sequence without WCK clock stop:

Enable training mode via MRS and wait tMRD

Sweep and observe the phase independently for WCK01 on EDC0 and WCK23 on EDC2; in case

the internal divide‐by‐2 circuits are at opposite phase use either the WCK01 or WCK23 inversion

bit

to flip one of the WCK divide‐by‐2 circuits

Adjust the WCK phase independently for WCK01 and WCK23 to the optimal point (“ideal 

alignment”)

Issue a PLL reset and wait for tLK (PLL on mode only)

While all WCK and CK are aligned, exit WCK2CK training mode via MRS

Wait tMRD for the reset of data synchronizers

Table 12 WCK2CK training simplified for Normal mode and PIN mode

High Frequency

Low Frequency

Frequency

≥ 2Gbps

＜ 2Gbps

WCK2CK alignment mode

Normal

Phase Search

Required

No*

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