 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
H5GQ2H24AFR-R0C 数据表(PDF) 41 Page - Hynix Semiconductor |
|
|
|||||||||||||||||||||||||||||
H5GQ2H24AFR-R0C 数据表(HTML) 41 Page - Hynix Semiconductor |
|
|
41 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 41 H5GQ2H24AFR 4. MODE REGISTERS GDDR5 specifies 10 Mode Registers to define the specific mode of operation. MR0 to MR7 and MR15 are defined as shown in the overview in Figure 22. MR8 to MR13 are not defined and may be used by DRAM vendors for vendor specific features. Repro- gramming the Mode Registers will not alter the contents of the memory array. All Mode Registers are programmed via the MODE REGISTER SET (MRS) command and will retain the stored information until they are reprogrammed or the device loses power. Mode Registers must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. No default states are defined for Mode Registers except when otherwise noted. Users therefore must fully initialize all Mode Reg- isters to the desired values e.g. upon power-up. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are reserved for future use and must be programmed to 0. Bit A12 is not used for any mode register programming as this address input is not defined for 512M and 1G density. BA3 BA2 BA1 BA0 A1 2/ 13 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MR0 00 00 0 Write Recovery (WR) TM CAS Latency (CLmrs) Write Latency (WLmrs) MR1 00 01 0 PLL Reset ABI WDBI RDBI PLL Cal Upd ADR/CMD Termination Data Termination Driver Strength MR2 00 10 0 ADR/CMD Termination Offset Data and WCK Termination Offset OCD Pullup Driver Offset OCD Pulldown Driver Offset MR3 00 11 0 Bank Groups WCK Termination Info RDQS Mode WCK 2CK WCK 23Inv WCK 01Inv Self Refresh MR4 01 00 0 EDC 13Inv WR CRC RD CRC CRC Read Latency (CRCRL) CRC Write Latency (CRCWL) EDC Hold Pattern MR5 01 01 0 RFU PLL Bandwidth (PLLBW) LP3 LP2 RFU MR6 01 10 0 VREFD Offset Upper 2 bytes VREFD Offset Lower 2 bytes VREFD Auto VREFD VREFD Merge WCK PIN MR7 01 11 0 DCC RFU Half VREFD Temp Sense DQ PreA Auto Sync LF Mode RFU PLL Stdby MR8 10 00 0 RFU MR9 10 01 0 RFU Pre & De ‐ Emphasis MR15 11 11 0 RFU ADT MRE MF1 MRE MF0 XX XX XX X X Figure 22. Mode Registers Overview |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
