H5GQ2H24AFR-R0C datasheet(100/172 Pages) HYNIX

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Rev. 1.2 /Nov. 2011

100

H5GQ2H24AFR

5.11. READ and WRITE DATA BUS INVERSION (DBI)

The GDDR5 SGRAM Data Bus Inversion (DBIdc) reduces the DC power consumption on data pins, as the

number of DQ lines driving a low level can be limited to 4 within a byte. DBIdc is evaluated per byte.

There is one DBI# pin per byte: DBI0# is associated with DQ0‐DQ7, DBI1# with DQ8‐DQ15, DBI2# with

DQ16‐DQ23 and DBI3# with DQ24‐DQ31.

The DBI# pins are bidirectional active Low double data rate (DDR) signals. For Writes, they are sampled

by the GDDR5 SGRAM along with the DQ of the same byte. For Reads, they are driven by the GDDR5

SGRAM along with the DQ of the same byte.

Once enabled by the corresponding RDBI Mode Register bit, the GDDR5 SGRAM inverts read data and

sets DBI# Low, when the number of ’0’ data bits within a byte is greater than 4; otherwise the GDDR5

SGRAM does not invert the read data and sets DBI# High, as shown in Figure 65.

Once enabled by the corresponding WDBI Mode Register bit, the GDDR5 SGRAM inverts write data

received on the DQ inputs in case DBI# was sampled Low, or leaves the data non‐inverted in case DBI#

was sampled High, as shown in Figure 66.

Figure 65. Example of Data Bus Inversion Logic for READs

Figure 66. Example of Data Bus Inversion Logic for WRITEs

The flow diagram in Figure 67 illustrates the DBIdc operation. In any case, the transmitter (the controller

for WRITEs, the GDDR5 SGRAM for READs) decides whether to invert or not invert the data conveyed on

the DQs. The receiver (the GDDR5 SGRAM for WRITEs, the controller for READs) has to perform the

reverse operation based on the level on the DBI# pin. Data input and output timing parameters are only

valid with DBI being enabled and a maximum of 4 data lines per byte driven Low.

from

DRAM

core

from Mode Register:

0 = enabled

1 = disabled

DBI#

’0’

count

DRAM

core

DBI#

from Mode Register:

0 = enabled

1 = disabled

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