H5GQ2H24AFR-R0C datasheet(70/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

5.6. BANK RESTRICTIONS

There may be a need to limit the number of activates in a rolling window to ensure that the instantaneous

current supplying capability of the devices is not exceeded. To reflect the short term capability of the

GDDR5 SGRAM current supply, the parameter tFAW (four activate window) is defined. No more than 4

banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by

tCK (ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds

up to 10 clocks, and an ACTIVE command is issued at clock N, no more than three further ACITIVE com‐

mands may be issued at clocks N+1 through N+9 as illustrated in Figure 41.

To reflect a longer term GDDR5 SGRAM current supply capability, the parameter t32AW (thirty‐two acti‐

vate window) is defined. No more than 32 banks may be activated in a rolling t32AW window. Converting

to clocks is done by dividing t32AW (ns) by tCK (ns) and rounding up to next integer value. The use of a

shorter and longer rolling activation window allows the GDDR5 SGRAM design to be optimized to handle

higher instantaneous currents within a shorter window while still limiting the current strain over a longer

period of time. This means that in general t32AW will be greater than or equal to 8* tFAW as shown in

Figure42.

It is preferable that GDDR5 SGRAMs have no rolling activation window restrictions (tFAW = 4 * tRRD).

Figure 41. tRRD and tFAW

ACT

tRRD

tFAW

tFAW +3 * t

ACT

RRD

CK#

CMD

tRRD = tRRDL or tRRDS depending on Bank Groups on/off setting and accessed banks

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