H5GQ2H24AFR-R0C datasheet(25/172 Pages) HYNIX

25 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

3.3. WCK2CK TRAINING

The purpose of WCK2CK training is to align the data WCK clock with the command CK clock to aid in the

GDDR5 SGRAM’s internal data synchronization between the logic clocked by CK/CK# and WCK/WCK#.

This will help to define both Read and Write latencies between the GDDR5 SGRAM and memory control‐

ler. WCK2CK training mode is controlled via MRS.

Before starting WCK2CK training, the following conditions must be met:

•CK/CK# clock is stable and toggling

•The timing of all address and command pins must be guaranteed

•PLL on/off(MR1 bit A7) and PLL delay compensation enable(MR7 bit A2) are set to desired mode before WCK to

CK training is started

•The desired WCK2CK alignment point (MR6, bit A0) is selected

•The EDC hold pattern (MR4, bits A0‐A3) must be programmed to ‘1111’

•2 Mode Register bits for internal WCK01 and WCK23 inversion (MR3, bits A2‐A3) must be set to a known state

•All banks are idle and no other command execution is in progress

WCK2CK training must be done after any of the following conditions:

•Device initialization

•Any CLmrs, WLmrs, CRCRL or CRCWL latency change

•CK and WCK frequency changes

•PLL on/off(MR1 bit A7) and PLL delay compensation mode(MR7 bit A2) changes

• Change of the WCK2CK alignment point (MR6, bit A0)

•WCK state change from off to toggling, including self refresh exit or exit from power‐down when bit A1 (LP2) in

MR5 is set

Figure 10 and Figure 11 show example WCK2CK training sequences. WCK2CK training is entered via

MRS by setting bit A4 in MR3. This will initiate the WCK divide‐by‐2 circuits associated with WCK01 and

WCK23 clocks in the GDDR5 SGRAM. In case the divide‐by‐2 circuits are at opposite output phases,

which is indicated by opposite “early/late” phases on the EDC pins associated with WCK01 and WCK23

(see below), they may be put in phase by using the WCK01 and WCK23 inversion bits. Alternatively, the

WCK clocks may be put into a stable inactive state for this initialization event to aid in resetting all divid‐

ers to the same output phase as shown in <Link>Figure 11. The challenge of this method is to restart the

WCK clocks in a way that even their first clock edges meet the WCK clock input specification. Otherwise,

divide‐by‐2 circuits for both WCK01 and WCK23 might again have opposite phase alignment.

Figure 12 illustrates how the WCK phase information is derived. The phase detectors (PD) sample the

internally divided‐by‐2 WCK clocks. Only one sample point is shown in the figure for clarity. In reality,

when WCK2CK training mode is enabled, a sample will occur every tCK and will be translated to the EDC

pins accordingly. If the divided‐by‐2 WCK clock arrives early, then the EDC pin outputs the EDC hold

pattern during the time interval specified in Figure 12. If the divided‐by‐2 WCK clock arrives late, then the

EDC pin outputs the inverted EDC hold pattern during the time interval specified in Figure 12. This is

shown in Table 11.

H5GQ2H24AFR-R0C 数据表(PDF) 25 Page - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 25 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载