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H5GQ2H24AFR-R0C 数据表(PDF) 93 Page - Hynix Semiconductor

部件名 H5GQ2H24AFR-R0C
功能描述  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 93 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
93
H5GQ2H24AFR
Figure 58. Single READ with EDC
EDC Hold Pattern
EDC Hold 
Pattern
EDC
EDC
n+7
n
Bank a,
Col n
Col n
CK
CK#
DQ
DBI#
CL = CLmrs = 6
T0
T1
T6
T7
T7n
T6n
T8
T10
T11
T12
T9
EDC
WCK#
CRCRL = 4
DONʹT CARE
TRANSITIONING DATA
DO
DO
DBI
DBI
n+7
n+7
n
n
WCK
3.  Before the READ command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
4.  tWCK2DQO = 0 is shown for illustration purposes.
1.  CLmrs = 6 and CRCRL = 4 are shown as examples.  Actual supported values will be found in the MR and AC timings sections.
2.  WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
Notes:
ADDRESS
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
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COMMAND
T10n
T11n



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