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H5GQ2H24AFR-R0C 数据表(PDF) 12 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 12 Page - Hynix Semiconductor |
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12 / 172 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 12 H5GQ2H24AFR 1.2. Initialization with Stable Power The following sequence is required for reset subsequent to power‐up initialization. This requires that the power has been stable within the specified VDD and VDDQ ranges since power‐up initialization (See Figure 4) 1) Assert RESET# Low anytime when reset is needed. 2) Hold RESET# Low for minimum 100ns. Assert and hold NOP command. 3) Set CKE# for the desired ADR/CMD ODT settings, then bring RESET# High to latch in the logic state of CKE#; tATS and tATH must be met during this procedure. Keep EDC1 (MF=0) / EDC2 (MF=1) at the same logic level as during power‐up initialization as device functionality is not guaranteed if the I/O width has changed. 4) Continue with step 9 of the power‐up initialization sequence. Figure 4: Initialization with Stable Power TRAIN / MRS ADR CKE# min. 100 ns CMD VDD, VDDQ VREFD/C RESET# tATS tATH DQ<31:0>, DBI#<3:0> ADR EDC<3:0> All Banks Precharge WCK NOP NOP CK# CK WCK# PRE NOP tRP Execution of steps 13‐21 in Power‐up sequence TRAIN / MRS TRAIN / MRS ADR A.C. ADR ADR min. 200 μs NOP NOP TRAIN / MRS A.C. ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) 2. Device functionality is not guaranteed if x32/x16 mode is not the same as during power‐up initialization. ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) Notes: 1. A.C. = Any Command |
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