H5GQ2H24AFR-R0C datasheet(22/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

3.2. ADDRESS TRAINING

The GDDR5 SGRAM provides means for address bus interface training. The controller may use the

address training mode to improve the timing margins on the address bus.

Address training mode is entered and exited via the ADT bit in Mode Register 15 (MR15). Mode Register

15 supports the same setup and hold times on the address pins as for commands to allow a safe entry into

address training mode.

Address training mode uses an internal bridge between the GDDR5 SGRAM’s address inputs and DQ/

DBI# outputs. It also uses a special READ command for address capture that is encoded using the SDR

command pins only (CS#,RAS#,CAS#,WE# = L,H,L,H). The address values normally used to encode the

commands will not be interpreted. Once the address training mode has been entered, the address values

registered coincident with this special READ command will be transmitted to the controller on the DQ/

DBI# pins. The controller is then expected to compare the address pattern received to the expected value

and to adjust the address transmit timing accordingly. The procedure may be repeated using different

address pattern and interface timings.

No WCK clock is required for this special READ command operation during address training mode. The

latched addresses are driven out asynchronously.

The only commands allowed during address training mode are this special READ, MRS (e.g. to exit

address training mode) and NOP / DESELECT.

When enabled by the ABI bit in Mode Register 1, address bus inversion (ABI) is effective during address

training mode. It is suggested to train the ABI# pin’s interface timing together with the other address lines.

The timing diagram in Figure 9 illustrates the typical command sequence in address training mode. The

DQ/DBI# output drivers are enabled as long as the ADT bit is set. The minimum spacing between consec‐

utive special READ commands is 2 tCK.

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