H5GQ2H24AFR-R0C datasheet(72/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

5.7. WRITE (WOM)

WRITE bursts are initiated with a WRITE command as shown in Figure 43. The bank and column

addresses are provided with the WRITE command and auto precharge is either enabled or disabled for

that access with the A8 pin. If auto precharge is enabled, the row being accessed is precharged at the com‐

pletion of the burst after tRAS(min) has been met. The length of the burst initiated with a WRITE command

is eight and the column address is unique for this burst of eight. There is no interruption nor truncation of

WRITE bursts.

Figure 43. WRITE Command

During WRITE bursts, the first valid data‐in element must be available at the input latch after the Write

Latency (WL). The Write Latency is defined as WLmrs * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQI, where

WLmrs is the number of clock cycles programed in MR0, tWCK2CKPIN is the phase offset between WCK

and CK at the pins when phase aligned at phase detector, tWCK2CK is the alignment error between WCK

and CK at the GDDR5 SGRAM phase detector, and tWCK2DQI is the WCK to DQ/DBI# offset as measured

at the DRAM pins to ensure concurrent arrival at the latch. The total delay is relative to the data eye center

averaged over one double‐byte. The maximum skew within a double‐byte is defined by tDQDQI.

The data input valid window, tDIVW, defines the time region when input data must be valid for reliable

data capture at the receiver for any one worst‐case channel. It accounts for jitter between data and clock at

the latching point introduced in the path between the DRAM pads and the latching point. Any additional

jitter introduced into the source signals (i.e. within the system before the DRAM pad) must be accounted

for in the final timing budget together with the chosen PLL mode and bandwidth. tDIVW is measured at

the pins. tDIVW is defined for the PLL off and on mode separately. In the case of PLL on, tDIVW must be

specified for each supported bandwidth. In general tDIVW is smaller than tDIPW.

A10,A11

0,0

CS#

WE#

CAS#

RAS#

CKE#

A9 (A12)

LOW

WRITE

CK#

A0,A6

BA0‐BA3

A2‐A5

EN AP

DIS AP

BA = Bank Address; CA = Column Address

EN AP = Enable Auto‐Precharge; DIS AP = Disable Auto‐Precharge

0,0

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