H5GQ2H24AFR-R0C datasheet(80/172 Pages) HYNIX

80 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

Figure 50. WRITE to PRECHARGE

2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

Bank a,

Col n

CK#

DBI#

WL = WLmrs = 3

WCK#

WCK

Ta0

Ta1

T3n

T4n

tWR

Bank a,

or all

tRP

DBI

n+7

1. WLmrs = 3 is shown as an example. Actual supported values will be found in the MR and AC timings sections.

3. EDC may be on or off. See Figure 4 for EDC Timing.

4. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.

5. Before the WRITE command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.

Notes:

6. tWCK2DQI = 0 is shown for illustration purposes.

DONʹT CARE

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