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H5GQ2H24AFR-R0C 数据表(PDF) 74 Page - Hynix Semiconductor

部件名 H5GQ2H24AFR-R0C
功能描述  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 74 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
74
H5GQ2H24AFR
Figure 44. WRITE Timings
CK
CK#
tCH
tCL
tCK
WLmrs
DQ/DBI#
(mean)
WCK#
WCK
tWCK2CKPIN + tWCK2CK
tWCK2DQI
DQ/DBI#
(first bit)
DQ/DBI#
(last bit)
tDQDQI(min)
tDQDQI(max)
1) WLmrs is the WRITE latency programmed in Mode Register MR0.
2) Timings are shown with positive tWCK2CKPIN and tWCK2CK values. See WCK2CK timings for 
tWCK2CKPIN and tWCK2CK ranges.
3) tWCK2DQI parameter values could be negative or positive numbers, depending on PLL‐on or PLL‐off mode  
operation and design implementation. They also vary across PVT. Data training is required to determine 
the actual tWCK2DQI value for stable WRITE operation.
4) tDQDQI defines the minimum to maximum variation of tWCK2DQI  within a double byte (x32 mode) or  
a single byte (x16 mode).
5) Data Read timings are used for CRC return timing from WRITE commands with CRC enabled.
D1 D2 D3 D4 D5 D6 D7
D0
D1 D2 D3 D4 D5 D6 D7
D0
D1 D2 D3 D4 D5 D6 D7
D0
Case 1: Negative tWCK2DQI
DQ/DBI#
(mean)
tWCK2DQI
DQ/DBI#
(first bit)
DQ/DBI#
(last bit)
tDQDQI(min)
tDQDQI(max)
D1 D2 D3 D4 D5 D6 D7
D0
D1 D2 D3 D4 D5 D6 D7
D0
D1 D2 D3 D4 D5 D6 D7
D0
Case 2: Positive tWCK2DQI
Donʹt Care



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