H5GQ2H24AFR-R0C datasheet(58/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

Separate Vref circuits are associated with the bytes in rows A to F and the bytes in rows M to U, with

separate VREFD pins for the required external Vref.

The only mandatory mode is that Vref will be supplied externally at the VREFD pins. This mode is

configured with bits A1‐A3 and bit A7 in MR7 all set to ’0’.

Figure 31. VREFD Options

VREFD Merge

The VREFD Merge mode is enabled when bit A1 is set to’1’. The externally supplied VFRED and the

internally generated Vref will be merged, resulting in the average value of both. DRAM vendor

specifications should be checked for values of external resistors that may be connected to VREFD pins in

this VREFD Merge mode.

Auto VREFD Training

When Auto is set for VREFD offsets, the internal Vref generator must be trained. Bit A2 enables this

training; the bit is self‐clearing, meaning that it returns back to the value ‘0’ after the training has

completed.

Once the training mode is enabled, the GDDR5 SGRAM drives the EDC pins Low to indicate to the

controller that the training has started. The controller is now expected to send the specified PRBS pattern

to the GDDR5 SGRAM. Upon completion of the training, the GDDR5 SGRAM stops driving the EDC pins

Low, and the EDC pins will resume transmitting the EDC hold pattern. But, it is not supported.

VREFD

Bit A3 selects between external and internal Vref. The bit is “Don’t Care” when VREFD Merge mode is

selected.

VREFD Offsets and VREFD Auto Mode

It supports the capability to offset Vref independently for the upper 2 bytes and the lower 2 bytes. The

offset step values may be non‐linear and will vary across PVT.

VREFD

0.5*VDDQ

0.7*VDDQ

‐

Receiver

DQ/DBI#

VREFD Offsets

VREFD

Half

VREFD

Merge

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