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H5GQ2H24AFR-R0C 数据表(PDF) 90 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 90 Page - Hynix Semiconductor |
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90 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 90 H5GQ2H24AFR A WRITE can be issued any time after a READ command as long as the bus turn around time tRTW is met. If that WRITE command is to another bank, then an ACTIVE command must precede the second WRITE command and tRCDWR also must be met. A PRECHARGE can also be issued to the GDDR5 SGRAM with the same timing restriction as the new READ command if tRAS is met. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The data inversion flag is driven on the DBI# pin to identify whether the data is true or inverted data. If DBI# is HIGH, the data is not inverted, and if LOW it is inverted. READ Data Inversion can be enabled (A8=0) or disabled (A8=1) using RDBI in MR1. |
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