H5GQ2H24AFR-R0C datasheet(89/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

5.9. READ

A READ burst is initiated with a READ command as shown in Figure 55. The bank and column addresses

are provided with the READ command and auto precharge is either enabled or disabled for that access

with the A8 address. If auto precharge is enabled, the row being accessed is precharged at the completion

of the burst after tRAS(min) has been met. The length of the burst initiated with a READ command is eight

and the column address is unique for this burst of eight. There is no interruption nor truncation of READ

bursts.

Figure 55. READ Command

During READ bursts, the first valid data‐out element will be available after the CAS latency (CL). The CAS

Latency is defined as CLmrs * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQO, where CLmrs is the number of

clock cycles programed in MR0, tWCK2CKPIN is the phase offset between WCK and CK at the pins when

phase aligned at phase detector, tWCK2CK is the alignment error between WCK and CK at the GDDR5

SGRAM phase detector, and tWCK2DQO is the WCK to DQ/DBI#/EDC offset as measured at the DRAM

pins. The total delay is relative to the data eye initial edge averaged over one double‐byte. The maximum

skew within a double‐byte is defined by tDQDQO.

Upon completion of a burst, assuming no other READ command has been initiated, all DQ and DBI# pins

will drive a value of ʹ1ʹ and the ODT will be enabled at a maximum of 1 tCK later. The drive value and ter‐

mination value may be different due to separately defined calibration offsets. If the ODT is disabled, the

pins will drive Hi‐Z.

Data from any READ burst may be concatenated with data from a subsequent READ command. A contin‐

uous flow of data can be maintained. The first data element from the new burst follows the last element of

a completed burst. The new READ command should be issued after the previous READ command accord‐

ing to the tCCD timing. If that READ command is to another bank then an ACTIVE command must pre‐

cede the READ command and tRCDRD also must be met.

WE#

A10,A11

0,0

CS#

CAS#

RAS#

CKE#

A9 (A12)

LOW

READ

CK#

A0,A6

BA0‐BA3

A2‐A5

EN AP

DIS AP

BA = Bank Address; CA = Column Address

EN AP = Enable Auto‐Precharge; DIS AP = Disable Auto‐Precharge

0,0

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