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H5GQ2H24AFR-R0C 数据表(PDF) 50 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 50 Page - Hynix Semiconductor |
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50 / 172 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 50 H5GQ2H24AFR 4.4. MODE REGISTER 3 (MR3) Mode Register 3 controls functions including Bank Groups, WCK termination, self refresh, RDQS mode, DRAM Info and WCK2CK training as shown in Figure 27. Mode Register 3 is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=1, BA2=0 and BA3=0. Figure 27. Mode Register 3 (MR3) Definition Self Refresh The refresh interval in self refresh mode may be set to 32ms, 16ms and 8ms. WCK2CK Bit A4 (WCK2CK) enables and disables the WCK2CK alignment training. For details on this training sequence, see the section on TRAINING. A1 A0 Self Refresh 00 32 ms 0 1 16ms 10 8ms 11 RFU BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 00 11 0 Bank Groups WCK Termination Info RDQS Mod e WCK 2CK WCK 23Inv WCK 01Inv Self Refresh A9 A8 WCK Termination 00 Disabled 01 ZQ/2 10 ZQ 11 RFU A4 WCK2CK Training 0Off 1On A3 WCK23 Invert 0Off 1On A2 WCK01 Invert 0Off 1On A7 A6 DRAM Info 00 off 01 Vendor ID 1 0 Temperature Readout 11 RFU A5 RDQS Mode 0Off 1On A11 A10 Bank Groups 0X off / tCCDL = 2 tCK 1X on / tCCDL = 3 tCK |
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