H5GQ2H24AFR-R0C datasheet(21/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

3. TRAINING

3.1. INTERFACE TRAINING SEQUENCE

Due to the high data rates of GDDR5, it is recommended that the interfaces be trained to operate with the

optimal timings. GDDR5 SGRAM has features defined which allow for complete and efficient training of

the I/O interface without the use of the GDDR5 SGRAM array. The interface trainings are required for nor‐

mal DRAM functionality unless running in lower frequency modes as described in the low frequency sec‐

tion. Interface timings will only be guaranteed after all required trainings have been executed.

A recommended order of training sequences has been chosen based on the following criteria:

The address training must be done first to allow full access to the Mode Registers. (MRS for address train‐

ing is a special single data rate mode register set guaranteed to work without training). Address input tim‐

ing shall function without training as long as tAS/H are met at the GDDR5 SGRAM.

WCK2CK training should be done before read training because a shift in WCK relative to CK will cause a

shift in all READ timings relative to CK.

READ training should be done before WRITE training because optimal WRITE training depends on cor‐

rect READ data.

Figure 8: Interface Training Sequence

Initialization

Address Training (optional)

WCK2CK Alignment Training

READ Training

WRITE Training

Start Normal Operation

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