H5GQ2H24AFR-R0C datasheet(64/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

4.10 MODE REGISTER 15 (MR15)

Mode Register 15 controls address training mode (ADT) and access to Mode Registers 0 to 14 (MRE) as

shown in Figure 34.

The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=1, BA2=1

and BA3=1.

Mode Register 15 is a special register that operates in SDR addressing mode. Increased setup and hold

times as for command inputs are assumed to ensure the MRS command to this register is successful while

address training (ADT) has not taken place and the integrity of DDR addresses may not be guaranteed.

This is indicated by setting bits A0‐A7 to Don’t Care (“X”) which are paired with the usable bits (A8‐A11)

and the Mode Register address (BA0‐BA3).

Figure 34. Mode Register 15 (MR15) Definition

Address Training (ADT)

Address training mode is enabled and disabled with bit A10.

Mode Register 0‐14 Enable

When disabled by bit A8 (for SGRAMs configured to MF=0) or bit A9 (for SGRAMs configured to MF=1),

the GDDR5 SGRAM will ignore any MODE REGISTER SET command to Mode Registers 0 to 14. If

enabled, MODE REGISTER SET commands function as normal. MODE REGISTER SET commands to

Mode Register 15 (this register) are not affected and will always be executed.

This functional allows for individual configuration of two GDDR5 SGRAMS on a common address bus

without the use of a CS# pin.

MR0‐14 Enable MF=1

0Enabled

Disabled

BA3 BA2 BA1 BA0

A12

A11

A10

RFU ADT MRE

MF1

MRE

MF0

A10 Address Training (ADT)

0Off

1On

MR0‐14 Enable MF=0

0Enabled

Disabled

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