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H5GQ2H24AFR-R0C 数据表(PDF) 95 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 95 Page - Hynix Semiconductor |
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95 / 172 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 95 H5GQ2H24AFR Figure 60. Gapless READs CL = CLmrs = 6 Bank a, Col m Col m CK CK# DQ DBI# WCK# WCK T7 T9 T10 T0 T1 T2 T3 T9n T6 T6n T7n T8 T8n DONʹT CARE TRANSITIONING DATA Bank b, Col n Col n DO DO DBI DBI m+7 m+7 m m tCCD DO DO n+7 n DBI DBI n+7 n 2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK. 4. tCCD = tCCDS when bank groups are disabled or the second READ is to a different bank group; otherwise tCCD=tCCDL. 5. Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met. 1. CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections. 3. EDC may be on or off. See Figure 58 for EDC Timing. Notes: 6. tWCK2DQI = 0 is shown for illustration purposes. NOP READ READ NOP NOP NOP NOP NOP NOP COMMAND ADDRESS ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) |
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