H5GQ2H24AFR-R0C datasheet(68/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

Figure 38. Mode Register Set Timings

5.5. ACTIVATION

Before any READ or WRITE commands can be issued to a bank in the GDDR5 SGRAM, a row in that bank

must be “opened”. This is accomplished by the ACTIVE command (see Figure 39): BA0 ‐BA3 select the

bank, and A0‐A12 select the row to be activated. Once a row is open, a READ or WRITE command could

be issued to that row, subject to the tRCD specification.

A subsequent ACTIVE command to another row in the same bank can only be issued after the previous

row has been closed (precharged). The minimum time interval between two successive ACTIVE com‐

mands on the same bank is defined by tRC. A minimum time, tRAS, must have elapsed between opening

and closing a row.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed,

which results in a reduction of total row‐access overhead. The minimum time interval between two suc‐

cessive ACTIVE commands on different banks to different bank groups is defined by tRRDS. With bank

groups enabled, the minimum time interval between two successive ACTIVE commands to different

banks in the same bank group is defined by tRRDL. In all other cases the interval is defined by tRRDS.

<Link>Figure shows the tRCD and tRRD definition.

CK#

CMD

A.C. = any command allowed in bank idle state

tRP

tMRD

Updating Setting

New Setting

Old Setting

NOP

PRE

ALL

NOP

MRS

NOP

A.C.

NOP

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