H5GQ2H24AFR-R0C datasheet(47/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

Calibration Update

The Calibration Update setting enables the calibration value to be updated automatically by the auto

calibration engine. The function is enabled upon power‐up to reduce update induced jitter. The user may

decide to suppress updates from the auto calibration engine by disabling Calibration Update (A6=1).

The calibration updates can occur with any REFRESH command. The update is not complete for a time

tKO after the latching of the REFRESH command. During this tKO time, only NOP or DESELECT

commands may be issued

PLL and PLL Reset

If a PLL is to be used, it must be enabled for normal operation by setting bit A7 to ’1’.

A PLL reset is done by turning the PLL off then on, or by use of the PLL Reset bit A11. The PLL Reset bit

is self clearing meaning that it returns back to the value ‘0’ after the PLL reset function has been issued.

RDBI and WDBI

Bit A8 controls Data Bus Inversion (DBI) for READs (RDBI), and bit A9 controls Data Bus Inversion for

WRITEs (WDBI). For more details on DBI see READ and WRITE Data Bus Inversion (DBI) in the section

entitled OPERATION.

ABI

Address Bus Inversion (ABI) is selected independently from DBI using bit A10. When enabled any data

sent over the address bus (whether opcode, addresses, LDFF data or DM) is inverted or not inverted based

on the state of ABI# signal. For more details on ABI see Address Bus Inversion (ABI) in the section entitled

OPERATION.

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