H5GQ2H24AFR-R0C datasheet(16/172 Pages) HYNIX

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Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

2.2. ADDRESS BUS INVERSION (ABI)

Address Bus Inversion (ABI) reduces the power requirements on address pins, as the no. of address lines

driving a low level can be limited to 4 (in case A12 is not wired) or 5 (in case A12 is wired).

The Address Bus Inversion function is associated with the electrical signalling on the address lines

between a controller and the GDDR5 SGRAM, regardless of whether the information conveyed on the

address lines is a row or column address, a mode register op‐code, a data mask, or any other pattern.

The ABI# input is an active Low double data rate (DDR) signal and sampled by the GDDR5 SGRAM at the

rising edge of CK and the rising edge of CK# along with the address inputs.

Once enabled by the corresponding ABI Mode Register bit, the GDDR5 SGRAM will invert the pattern

received on the address inputs in case ABI# was sampled Low, or leave the pattern non‐inverted in case

ABI# was sampled High, as shown in Figure 6.

Figure 6: Example of Address Bus Inversion Logic

8 (9)

DRAM

core

ABI#

Address

Pins

from Mode Register:

0 = enabled

1 = disabled

Note: bus width is 8 when A12/RFU pin is not present, and 9 when A12/RFU pin is present

Note : Bus width is 8 when A12 is not present, and 9 when A12 is present.

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