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H5GQ2H24AFR-R0C 数据表(PDF) 26 Page - Hynix Semiconductor

部件名 H5GQ2H24AFR-R0C
功能描述  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 26 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
26
H5GQ2H24AFR
Figure 10: Example WCK2CK Training Sequence
Figure 11: Example WCK2CK Training Sequence with WCK Stopping
CK
CK#
NOP
NOP
MRS
NOP
NOP
NOP
NOP
MRS
MRS
CMD
A.C.
tLK
tMRD
Enter WCK2CK Training
Start WCK2CK 
Phase Search
PLL Reset 
Exit WCK2CK Training
(sets data synchronizers, 
rests FIFO pointers)
WCK
WCK#
(PLL on only)
NOP
MRS
NOP
NOP
NOP
NOP
MRS
NOP
NOP
Valid
MRS
CK#
CK
CMD
tWCK2MRS
WCK
WCK#
tMRSTWCK
tWCK2TR
Enter WCK2CK
Training by MRS
WCK
Restart
Start WCK2CK
Phase Search
tLK
tMRD
Exit WCK2CK 
(resets WCK divide‐
 by‐2 circuits)
resets FIFO pointers)
(Set data synchronizers, 
Training by MRS
PLL Reset 
(PLL on only)



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