H5GQ2H24AFR-R0C datasheet(10/172 Pages) HYNIX

10 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

1. INITIALIZATION

1.1. POWER‐UP SEQUENCE

GDDR5 SGRAMs must be powered up and initialized in a predefined manner as shown below. Operational proce-

dures other than those specified may result in undefined operation. The Mode Registers do not have RESET default

values, except for ABI#, ADR/CMD termination, and the EDC hold pattern. If the mode registers are not set during the

initialization sequence, it may lead to unspecified operation.

Step

Apply power to VDD

Apply power to VDDQ at same time or after power is applied to VDD

Apply VREFC and VREFD at same time or after power is applied to VDDQ

After power is stable, provide stable clock signals CK/CK#

Assert and hold RESET# low to ensure all drivers are in Hi‐Z and all active terminations are off. Assert and hold NOP command.

Wait a minimum of 200μs.

If boundary scan mode is necessary, SEN can be asserted HIGH to enter boundary scan mode. Boundary scan mode must be

entered directly after power‐up while RESET# is low. Once boundary scan is executed, power‐up sequence should be followed.

Set CKE# for the desired ADR/CMD ODT settings, then bring RESET# High to latch in the logic state of CKE#, tATS and tATH must

be met during this procedure. See Table 1 for the values and logic states for CKE#. The rising edge of RESET# will determine x32

mode or x16 mode depending on the state of EDC1(EDC2 when MF=1). In normal x32 mode, EDC1 has to be sustained HIGH until

RESET# is HIGH. See Table 57 for the values and logic states for EDC1(EDC2 when MF=1).

Bring CKE# Low after tATH is satisfied

Wait at least 200μs referenced from the beginning of tATS

Issue at least 2 NOP commands

Issue a PRECHARGE ALL command followed by NOP commands until tRP is satisfied

Issue MRS command to MR15. Set GDDR5 SGRAM into address training mode (optional)

Complete address training (optional)

Issue MRS command to read the Vendor ID

Issue MRS command to set WCK01/WCK01# and WCK23/WCK23# termination values

Provide stable clock signals WCK01/WCK01# and WCK23/WCK23#

Issue MRS commands to use PLL or not and select the position of a WCK/CK phase detector. The use of PLL and the position of a

phase detector should be issued before WCK2CK training. Issue MRS commands including PLL reset to the mode registers in any

order. tMRD must be met during this procedure. WLmrs, CLmrs, CRCWL and CRCRL must be programmed before WCK2CK

training.

Issue two REFRESH commands followed by NOP until tRFC is satisfied

After any necessary GDDR5 training sequences such as WCK2CK training, READ training (LDFF, RDTR) and WRITE training

(WRTR, RDTR), the device is ready for operation.

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