H5GQ2H24AFR-R0C datasheet(31/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

GDDR5 WCK2CK Training in x16 mode

For configurations with WCK clocks not shared between two GDDR5 SGRAMs it is suggested to set the

WCK phase to the ideal alignment point. However, for configurations where two GDDR5 SGRAMs (x16)

share their WCK clocks as in a x16 clamshell, an offset given by the midpoint of both DRAM’s ideal WCK

positions may be required. The maximum allowed offset in this case is specified by parameter

tWCK2CKSYNC: it defines the WCK offset range from the ideal alignment which still guarantees a GDDR5

SGRAM device to internally synchronize its WCK and CK clocks upon training exit.

Example: outline of training sequence for x32 and x16 configurations with 2 GDDR5 SGRAMs sharing

their WCK clocks (e.g. clamshell)

Enable training mode for both DRAMs via MRS and wait tMRD

For both DRAMs sweep and observe the phase independently for WCK01 on EDC0 and WCK23

on 

EDC2; in case the internal divide‐by‐2 circuits are at opposite phases use either the WCK01 or 

WCK23 inversion bit to flip one of the WCK divide‐by‐2 circuits; in case of shared CS# signals use 

MREMF0 and MREMF1 bits in MR15 to explicitly direct the MRS command for this phase flipping 

to either DRAM1 or DRAM2 (“soft chip select”);

Sweep and observe the phase on DRAM1 independently for WCK01 on EDC0 and WCK23 on 

EDC2; store the setting for the optimal WCK phase

Sweep and observe the phase on DRAM2 independently for WCK01 on EDC0 and WCK23 on 

EDC2; store the setting for the optimal WCK phase

Sweep WCK01 and WCK23 phase to midpoint of DRAM1 and DRAM2 optimal settings

Issue a PLL reset and wait for tLK (PLL on mode only)

While all WCK and CK are aligned, exit WCK2CK training mode via MRS

Wait tMRD for the reset of data synchronizers

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