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H5GQ2H24AFR-R0C 数据表(PDF) 42 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 42 Page - Hynix Semiconductor |
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42 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 42 H5GQ2H24AFR 4.1. MODE REGISTER 0 (MR0) Mode Register 0 controls operating modes such as Write Latency, CAS latency, Write Recovery and Test Mode as shown in Figure 23. The register is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=0, BA2=0 and BA3=0. BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 00000 Write Recovery (WR) TM CAS Latency (CLmrs) Write Latency (WLmrs) A11 A10 A9 A8 Write Recovery (WR) 0 000 4 0 001 5 0 010 6 0 011 7 0 100 8 0 101 9 0 110 10 0 111 11 1 000 12 1 001 13 1 010 14 1 011 15 1 100 16 1 101 17 1 110 18 1 111 19 A7 Test Mode 0Normal 1Test Mode A2 A1 A0 Write Latency (WLmrs) 00 0 RFU 00 1 1 01 0 2 01 1 3 10 0 4 10 1 5 11 0 6 11 1 7 A6 A5 A4 A3 CAS Latency (CLmrs) 0000 5 0001 6 0010 7 0011 8 0100 9 0101 10 0110 11 0111 12 1000 13 1001 14 1010 15 1011 16 1100 17 1101 18 1110 19 1111 20 Figure 23. Mode Register 0 (MR0) Definition |
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