H5GQ2H24AFR-R0C datasheet(73/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

The data input pulse width, tDIPW, defines the minimum positive or negative input pulse width for any

one worst‐case channel required for proper propagation of an external signal to the receiver. tDIPW is mea‐

sured at the pins. tDIPW is independent of the PLL mode. In general tDIPW is larger than tDIVW.

Upon completion of a burst, assuming no other WRITE data is expected on the bus the GDDR5 SGRAM

DQ and DBI# pins will be driven according to the ODT state. Any additional input data will be ignored.

Data for any WRITE burst may not be truncated with a subsequent WRITE command.

Data from any WRITE burst may be concatenated with data from a subsequent WRITE command. A con‐

tinuous flow of data can be maintained. The first data element from the new burst follows the last element

of a completed burst. The new WRITE command should be issued after the previous WRITE command

according to the tCCD timing. If that WRITE command is to another bank then an ACTIVE command must

precede the WRITE command and tRCDWR also must be met.

A READ can be issued any time after a WRITE command as long as the internal turn around time tWTR is

met. If that READ command is to another bank, then an ACTIVE command must precede the READ com‐

mand and tRCDRD also must be met.

A PRECHARGE can also be issued to the GDDR5 SGRAM with the same timing restriction as the new

WRITE command if tRAS is met. After the PRECHARGE command, a subsequent command to the same

bank cannot be issued until tRP is met.

The data inversion flag is received on the DBI# pin to identify whether to store the true or inverted data. If

DBI# is LOW, the data will be stored after inversion inside the GDDR5 SGRAM and not inverted if DBI# is

HIGH. WRITE Data Inversion can be enabled (A9=0) or disabled (A9=1) using WDBI in MR1.

When enabled by the WRCRC flag in MR4, EDC data are returned to the controller with a latency of

(WLmrs + CRCWL) * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQO, where CRCWL is the CRC Write latency

programmed in MR4 and tWCK2DQO is the WCK to DQ/DBI#/EDC phase offset at the DRAM pins.

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