H5GQ2H24AFR-R0C datasheet(102/172 Pages) HYNIX

102 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

102

H5GQ2H24AFR

5.12. ERROR DETECTION CODE (EDC)

The GDDR5 SGRAM provides error detection on the data bus to improve system reliability. The device

generates a checksum per byte lane for both READ and WRITE data and returns the checksum to the con‐

troller. Based on the checksum, the controller can decide if the data (or the returned CRC) was transmitted

in error and retry the READ or WRITE command. The GDDR5 SGRAM itself does not perform any error

correction. The features of the EDC are:

•8 bit checksum on 72 bits (9 channels x 8 bit burst)

• dedicated EDC transfer pin per 9 channels (4x per GDDR5 SGRAM)

•asymmetrical latencies on EDC transfer for Reads and Writes

The CRC polynomial used by the GDDR5 SGRAM is an ATM‐8 HEC, X^8+X^2+X^1+1. The starting seed

value is set in hardware at “zero”. Table 24 shows the error types that are detectable and the detection rate.

The bit ordering calculation for the CRC error detection is optimized for errors in the time burst direction.

Figure 68 shows the bit orientation on a byte lane basis.

Table 24 Error Correction Details

Error Type

Detection Rate

Random Single Bit

100%

Random Double Bit

100%

Random Odd Count

100%

Burst <= 8100%

H5GQ2H24AFR-R0C 数据表(PDF) 102 Page - Hynix Semiconductor