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DRV8461SPWPR 数据表(PDF) 29 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 29 Page - Texas Instruments |
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29 / 117 page  Use Equation 1 to calculate the full-scale regulation current for H/W interface. IFS (A) = VREF (V) / KV (V/A) (1) For the SPI interface, the 8-bit TRQ_DAC register further scales the full-scale current as shown in Equation 1. See Table 7-16 for TRQ_DAC settings. IFS (A) = VREF (V) x TRQ_DAC / KV (V/A) (2) Table 7-16. TRQ_DAC Settings TRQ_DAC CURRENT SCALAR 11111111b 100% 11111110b 99.61% 11111101b 99.22% 11111100b 98.83% ........ ........ 00000000b 0.39% Another 8-bit register ISTSL programs the holding current (IHOLD) when STEP pulses are not applied and the motor is being held at same position. Transitioning to a lower value of holding current reduces motor and driver power loss. See Section 7.3.13 for details. IHOLD (A) = VREF (V) x ISTSL / KV (V/A) (3) Table 7-17. ISTSL Settings ISTSL Holding Current Value 11111111b 100% 11111110b 99.61% 11111101b 99.22% 11111110b 98.83% ........ ........ 00000000b 0.39% Note Always set ISTSL to a value lower than the TRQ_DAC value. 7.3.8.1 Internal Reference Voltage When operating with the SPI interface, the DRV8461 supports an internal 3.3 V reference voltage. This internal reference can be enabled by writing 1b to the VREF_INT_EN bit. The voltage on the VREF pin will be ignored in that case, and the VREF pin can be left open or connected to ground. The full-scale current and the holding current will be calculated as shown in Equation 4 and Equation 5 - IFS (A) = 3.3 V x TRQ_DAC / KV (V/A) (4) IHOLD (A) = 3.3 V x ISTSL / KV (V/A) (5) Using the internal 3.3 V as reference will save BOM cost by eliminating the two resistors connected to the VREF pin. www.ti.com DRV8461 SLOSE98 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DRV8461 |
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