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DRV8461SPWPR 数据表(PDF) 6 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 6 Page - Texas Instruments |
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6 / 117 page  PIN TYPE DESCRIPTION NAME DDW PWP SPI Interface H/W Interface ENABLE 41 25 Input Logic low to disable device outputs; logic high to enable. When the device operates with H/W interface, the ENABLE pin also determines the OCP, OL and OTSD fault recovery methods. nSLEEP 42 26 Input Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode. A narrow nSLEEP reset pulse clears latched faults. CPL 43 27 Power Charge pump switching node. Connect a X7R, 0.1-μF, VM- rated ceramic capacitor from CPH to CPL. CPH 44 28 Power PAD - - - Thermal pad. Connect to system ground. DRV8461 SLOSE98 – DECEMBER 2022 www.ti.com 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8461 |
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