DRV8461SPWPR datasheet(70/117 Pages) TI

70 / 117 page

keeps additional read commands for the MCU and makes the system more efficient to determine fault conditions

flagged in a device. Status bytes must start with 1 and 1 for the two MSBs.

Header Bytes

(HDRx)

Status Byte

(Sx)

Data Byte

(Dx)

Address Byte

(Ax)

CLR

UVLO

CPUV

OCP

STL

R/W

Figure 7-53. Contents of Header, Status, Address, and Data Bytes

When data passes through a device, it determines the position of itself in the chain by counting the number of

status bytes it receives followed by the first header byte. For example, in this 3-device configuration, device 2 in

the chain receives two status bytes before receiving the HDR1 byte which is then followed by the HDR2 byte.

From the two status bytes, the data can determine that its position is second in the chain. From the HDR2

byte, the data can determine how many devices are connected in the chain. In this way, the data only loads

the relevant address and data byte in its buffer and bypasses the other bits. This protocol allows for faster

communication without adding latency to the system for up to 63 devices in the chain.

The address and data bytes remain the same with respect to a 1-device connection. The report bytes (R1

through R3), as shown in Figure 7-51, are the content of the register being accessed.

MSB

LSB

MSB

LSB

nSCS

SCLK

SDI

SDO

Capture

Point

Propagate

Point

Figure 7-54. SPI Transaction

7.4.1.3 SPI for Multiple Target Devices in Parallel Configuration

Figure 7-55 shows three DRV8461 devices connected in parallel configuration.

DRV8461

SLOSE98 – DECEMBER 2022

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DRV8461SPWPR 数据表(PDF) 70 Page - Texas Instruments

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