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DRV8461SPWPR 数据表(PDF) 18 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 18 Page - Texas Instruments |
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18 / 117 page  7.3 Feature Description Table 7-1 lists the recommended external components for the DRV8461. Table 7-1. External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM PGNDA X7R, 0.01-µF, VM-rated ceramic capacitors CVM2 VM PGNDB X7R, 0.01-µF, VM-rated ceramic capacitors CVM3 VM PGNDA Bulk, VM-rated capacitor CVCP VCP VM X7R, 1-µF, 16-V ceramic capacitor CSW CPH CPL X7R, 0.1-µF, VM-rated ceramic capacitor CDVDD DVDD GND X7R, 1-µF, 6.3-V ceramic capacitor CVCC VCC GND X7R, 0.1-µF, 6.3-V ceramic capacitor RnFAULT DVDD or VCC nFAULT 10-kΩ resistor RnHOME DVDD or VCC nHOME 10-kΩ resistor RREF1 VREF DVDD or VCC Resistor to set chopping current. Not required if VREF_INT_EN = 1b. RREF2 VREF GND 7.3.1 Interface of Operation The DRV8461 can operate with hardware (H/W) pin interface or SPI. When operating with SPI, the device supports additional features and detailed diagnostics, as shown in Table 7-4. For the DDW package option, the logic-level MODE pin latches the operating interface information at power up or after nSLEEP cycling - • If the MODE pin is grounded at this time, the device operates with H/W pin interface. • If the MODE pin is logic high at this time, the device operates with SPI. Note Do not change MODE pin logic level on the fly after power up or after nSLEEP = 1. The functionality of five pins depend on the interface of operation, as shown in Table 7-2 and Table 7-3 - Table 7-2. Pin function, DDW package Pin Number H/W interface SPI Interface 34 M0 nSCS 35 TOFF Reserved 36 DECAY1 SDO 37 DECAY0 SDI 38 M1 SCLK Table 7-3. Pin function, PWP package Pin Number DRV8461SPWPR (SPI) DRV8461PWPR (H/W Interface) 18 nSCS M0 19 VCC TOFF 20 SDO DECAY1 21 SDI DECAY0 DRV8461 SLOSE98 – DECEMBER 2022 www.ti.com 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8461 |
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