DRV8461SPWPR datasheet(58/117 Pages) TI

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7.3.19.5 Stall Detection

When operating with the SPI interface, the DRV8461 supports stall detection.

Stepper motors have a distinct relation between the winding current, back-EMF, and mechanical torque load of

the motor, as shown in Figure 7-42. For an unloaded motor, the back-EMF is 90° out-of-phase with the winding

current. As motor load approaches the maximum torque capability of the motor for a given winding current, the

back-EMF will move in phase with the winding current. By detecting back-EMF phase shift between rising and

falling current quadrants of the motor current, the DRV8461 can detect a motor overload stall condition or an

end-of-line travel.

Figure 7-42. Stall Detection by Monitoring Motor Back-EMF

The Stall Detection algorithm is enabled when -

• The device is programmed to operate with the SPI interface (MODE = 1)

• The decay mode is programmed as smart tune Ripple Control (DECAY = 111b)

• EN_STL is 1b

• No fault condition exists (UVLO, OCP, OL, OTSD etc.).

The algorithm compares the back-EMF between the rising and falling current quadrants by monitoring PWM off

time and generates a parameter called torque count, represented by the TRQ_COUNT register. The comparison

is done in such a way that the TRQ_COUNT is largely independent of motor current, ambient temperature and

supply voltage. Motor stall can be detected even if the driver is operating in full step mode.

TRQ_COUNT is calculated as a running average from the most recent four electrical half-cycles. TRQ_COUNT

and if a stall condition is detected, stall fault will be reported and latched at the electrical half-cycle current zero

crossing.

For a lightly loaded motor, the TRQ_COUNT will be a non-zero value. As the motor approaches stall condition,

TRQ_COUNT will approach zero and can be used to detect stall condition.

• If anytime TRQ_COUNT falls below the stall threshold (represented by the STALL_TH register), the device

will detect a stall.

• STALL, STL and FAULT bits are latched 1b in the SPI register.

• The STL_REP bit controls how stall is reported.

– If STL_REP is 1b, the nFAULT pin will be driven low when a stall is detected.

– If STEL_REP is 0b, the nFAULT pin will stay high even if stall is detected.

DRV8461

SLOSE98 – DECEMBER 2022

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