DRV8461SPWPR datasheet(59/117 Pages) TI

59 / 117 page

In the stalled condition, the motor shaft does not spin. The motor starts to spin again when the stall condition is

removed and the motor ramps to its target speed. The nFAULT is released and the fault registers are cleared

when a clear faults command is issued either via the CLR_FLT bit or an nSLEEP reset pulse.

High motor coil resistance can result in low TRQ_COUNT. The TRQ_SCALE bit allows scaling up low

TRQ_COUNT values, for ease of further processing.

• If the initially calculated TRQ_COUNT value is less than 500 and the TRQ_SCALE bit is 1b, then the

TRQ_COUNT output in register is multiplied by a factor of 8.

• If the TRQ_SCALE bit is 0b, TRQ_COUNT retains the value originally calculated by the algorithm.

Stall threshold can be set in two ways –

• The user can write the STALL_TH bits by observing the behavior of the TRQ_COUNT output at all operating

conditions.

• The algorithm can learn the stall threshold using the automatic stall learning process, described below:

– Before learning, ensure that the motor has reached its target speed. Do not learn stall threshold while the

motor speed is ramping up or down.

– Start learning by setting the STL_LRN bit to 1b.

– Run motor with no load.

– Wait for 32 electrical cycles for the driver to learn the steady-state count.

– Stall the motor.

– Wait for 16 electrical cycles for the driver to learn the stall count.

– The STL_LRN_OK bit becomes 1b if learning is successful.

– Stall threshold is calculated as the average of steady count and stall count and stored in the STALL_TH

The flowchart on how to set stall threshold is shown below.

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DRV8461

SLOSE98 – DECEMBER 2022

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DRV8461SPWPR 数据表(PDF) 59 Page - Texas Instruments