DRV8461SPWPR datasheet(66/117 Pages) TI

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7.3.20 Device Functional Modes

7.3.20.1 Sleep Mode

When the nSLEEP pin is low, the device enters a low-power sleep mode. In sleep mode, all the internal

MOSFETs, the DVDD regulator, SPI and the charge pump is disabled. The tSLEEP time must elapse after a falling

edge on the nSLEEP pin before the device enters sleep mode. The device is brought out of sleep automatically if

the nSLEEP pin is brought high. The tWAKE time must elapse before the device is ready for inputs.

7.3.20.2 Disable Mode

The ENABLE pin is used to enable or disable the half bridges in the device. When the ENABLE pin is low, the

output drivers are disabled (Hi-Z). For operation with SPI interface, the EN_OUT bit can also be used to disable

the output drivers, as shown in Table 7-29. When the EN_OUT bit is 0b, the output drivers are disabled (Hi-Z).

Table 7-29. Conditions to Enable or Disable Output Drivers

nSLEEP

ENABLE

EN_OUT

H-BRIDGE

Disabled

Enabled

7.3.20.3 Operating Mode

This mode is enabled when -

• nSLEEP is high

• ENABLE pin is Hi-Z or logic high

• EN_OUT = 1b for SPI interface

• VM > UVLO

The tWAKE time must elapse before the device is ready for inputs.

7.3.20.4 nSLEEP Reset Pulse

A latched fault can be cleared by an nSLEEP reset pulse. This pulse width must be greater than 20 µs and

smaller than 40 µs. If nSLEEP is low for longer than 40 µs, but less than 120 µs, the faults are cleared and the

device may or may not shutdown, as shown in Figure 7-47. This reset pulse does not affect the status of the

charge pump or other functional blocks.

nSLEEP

All faults cleared,

device stays active

All faults cleared, device may or may not shutdown

Device shuts down (goes into sleep mode,

faults cleared by default)

20 µs

40 µs

120 µs

Figure 7-47. nSLEEP Reset Pulse

DRV8461

SLOSE98 – DECEMBER 2022

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