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DRV8461SPWPR 数据表(PDF) 65 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 65 Page - Texas Instruments |
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65 / 117 page  nFAULT pin can be tied to the DVDD pin with a resistor. For a 3.3-V or 1.8-V pullup, an external supply must be used. Output nFAULT Figure 7-46. nFAULT Pin 7.3.19.11 Fault Condition Summary Table 7-28. Fault Condition Summary FAULT CONDITION CONFIGURATION ERROR REPORT H- BRIDGE CHARGE PUMP INDEXER LOGIC RECOVERY VM undervoltage (UVLO) VM < VUVLO — nFAULT / SPI Disabled Disabled Disabled Reset VM > VUVLO VCP undervoltage (CPUV) VCP < VCPUV — nFAULT / SPI Disabled Operating Operating Operating VCP > VCPUV Logic Supply POR VCC < VCCUVLO — SPI Disabled Disabled Disbaled Reset VCC > VCCUVLO Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b / ENABLE = Hi-Z nFAULT / SPI Disabled Operating Operating Operating Latched: CLR_FLT / nSLEEP reset pulse OCP_MODE = 1b / ENABLE = 1 nFAULT / SPI Disabled Operating Operating Operating Automatic retry: tRETRY Open Load (OL) No load detected OL_MODE = 1b / ENABLE = 1 nFAULT / SPI Operating Operating Operating Operating Automatic OL_MODE = 0b / ENABLE = Hi-Z nFAULT / SPI Operating Operating Operating Operating Latched: CLR_FLT / nSLEEP reset pulse Stall Detection (STALL) Stall / stuck motor STL_REP = 0b SPI Operating Operating Operating Operating CLR_FLT / nSLEEP reset pulse STL_REP = 1b nFAULT / SPI Operating Operating Operating Operating Overtemperature Warning (OTW) TJ > TOTW TW_REP = 1b nFAULT / SPI Operating Operating Operating Operating Automatic: T J < TOTW - THYS_OTW TW_REP = 0b SPI Operating Operating Operating Operating Thermal Shutdown (OTSD) TJ > TOTSD OTSD_MODE = 0b / ENABLE = Hi-Z nFAULT / SPI Disabled Disabled Operating Operating Latched: CLR_FLT / nSLEEP reset pulse OTSD_MODE = 1b / ENABLE = 1 nFAULT/ SPI Disabled Disabled Operating Operating Automatic: TJ < TOTSD - THYS_OTSD www.ti.com DRV8461 SLOSE98 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: DRV8461 |
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