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DRV8461SPWPR 数据表(PDF) 71 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 71 Page - Texas Instruments |
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71 / 117 page  Microcontroller DRV8461 (3) DRV8461 (2) DRV8461 (1) SPI SPI SPI M-CS1 M-CS2 M-CS3 M-CLK M-SDO M-SDI SDI1 SDO1 SDI2 SDO2 SDI3 SDO3 Figure 7-55. Three Devices Connected in Parallel Configuration 7.5 Register Maps Table 7-33 lists the memory-mapped registers for the device. All register addresses not listed in Table 7-33 should be considered as reserved locations and the register contents must not be modified. Table 7-33. Memory Map Register 7 6 5 4 3 2 1 0 Type Address FAULT FAULT SPI_ERROR UVLO CPUV OCP STL TF OL R 0x00 DIAG1 OCP_LS2_B OCP_HS2_B OCP_LS1_B OCP_HS1_B OCP_LS2_A OCP_HS2_A OCP_LS1_A OCP_HS1_A R 0x01 DIAG2 STSL OTW OTS STL_LRN_OK STALL LRN_DONE OL_B OL_A R 0x02 DIAG3 RSVD NHOME CNT_OFLW CNT_UFLW RSVD NPOR RSVD R 0x03 CTRL1 EN_OUT SR IDX_RST TOFF [1:0] DECAY [2:0] RW 0x04 CTRL2 DIR STEP SPI_DIR SPI_STEP MICROSTEP_MODE [3:0] RW 0x05 CTRL3 CLR_FLT LOCK [2:0] TOCP OCP_MODE OTSD_MODE OTW_REP RW 0x06 CTRL4 TBLANK_TIME[1:0] STL_LRN EN_STL STL_REP STL_FRQ STEP_FRQ_TOL[1:0] RW 0x07 CTRL5 STALL_TH [7:0] RW 0x08 CTRL6 RC_RIPPLE[1:0] DIS_SSC TRQ_SCALE STALL_TH[11:8] RW 0x09 CTRL7 TRQ_COUNT [7:0] R 0x0A CTRL8 RSVD TRQ_COUNT[11:8] R 0x0B CTRL9 EN_OL OL_MODE OL_T[1:0] STEP_EDGE RES_AUTO[1:0] EN_AUTO RW 0x0C CTRL10 ISTSL[7:0] RW 0x0D CTRL11 TRQ_DAC[7:0] RW 0x0E CTRL12 EN_STSL TSTSL_FALL[3:0] RSVD RW 0x0F CTRL13 TSTSL_DLY[5:0] VREF_INT_EN RSVD RW 0x10 INDEX1 CUR_A_POS[7:0] R 0x11 INDEX2 CUR_A_SIGN RSVD R 0x12 INDEX3 CUR_B_POS[7:0] R 0x13 INDEX4 CUR_B_SIGN RSVD CUR_A[1:0] R 0x14 INDEX5 CUR_A[9:2] R 0x15 CUSTOM_CTRL1 RSVD EN_CUSTOM RW 0x16 www.ti.com DRV8461 SLOSE98 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: DRV8461 |
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