 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
DRV8461SPWPR 数据表(PDF) 55 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DRV8461SPWPR 数据表(HTML) 55 Page - Texas Instruments |
|
|
55 / 117 page  7.3.19 Protection Circuits The device is fully protected against supply undervoltage, charge pump undervoltage, output overcurrent, open load, and device overtemperature events. In addition, when operating with SPI interface, the device is protected against stall detection in the event of overload or end-of-line movement. 7.3.19.1 VM Undervoltage Lockout If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: • All the outputs are disabled (High-Z) • The charge pump is disabled • nFAULT is driven low Normal operation resumes (motor driver and charge pump) when the VM voltage recovers above the UVLO rising threshold voltage. When operating with SPI interface, if the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST or VCC UVLO (shown in Figure 7-39) : • SPI communication is available and the digital core of the device is active • The FAULT and UVLO bits are made 1b • The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: • nFAULT pin is released (is pulled-up to the external voltage) • The FAULT bit becomes 0b • The UVLO bit remains latched 1b until cleared through the CLR_FLT bit or an nSLEEP reset pulse. VRST UVLO reset or VCC UVLO VUVLO rising VUVLO falling Device Status SPI available Digital Alive Outputs switching CP enabled UVLO, FAULT bits 0b* nFAULT high Time VM Voltage * FAULT bit will be 0b if no fault is present ** UVLO bit will be 1b till cleared by CLR_FLT or nSLEEP pulse SPI available Digital Alive Outputs switching CP enabled UVLO bit 1b** FAULT bit 0b* nFAULT high SPI available Digital Alive Outputs Hi-Z CP disabled UVLO, FAULT bits 1b nFAULT low Figure 7-39. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST or VCC UVLO (shown in Figure 7-40) : • SPI communication is unavailable and the digital core is shutdown • The FAULT and UVLO bits are 0b • The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: • The digital core comes alive • UVLO bit stays at 0b • The FAULT bit is made 1b • The nFAULT pin is pulled low • When the VM voltage exceeds the VM UVLO rising threshold www.ti.com DRV8461 SLOSE98 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: DRV8461 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
