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DRV8461SPWPR 数据表(PDF) 80 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 80 Page - Texas Instruments |
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80 / 117 page  Table 7-47. CTRL7 Control Register Field Descriptions Bit Field Type Default Description 7-0 TRQ_COUNT[7:0] R 11111111b 8 LSB bits of TRQ_COUNT. 000000000000b = 0 count XXXXXXXXXXXXb = 1 to 4094 counts 111111111111b = 4095 counts 7.5.2.8 CTRL8 (address = 0x0B) [Default = 0Fh] CTRL8 is shown in Figure 7-67 and described in Table 7-48. Read-only Return to the Register Maps Table Figure 7-67. CTRL8 Control Register 7 6 5 4 3 2 1 0 RSVD TRQ_COUNT[11:8] R-0000b R-1111b Table 7-48. CTRL8 Control Register Field Descriptions Bit Field Type Default Description 7-4 RSVD R 0000b Reserved. 3-0 TRQ_COUNT[11:8] R 1111b 4 MSB bits of TRQ_COUNT. 7.5.2.9 CTRL9 (address = 0x0C) [Default = 10h] CTRL9 is shown in Figure 7-68 and described in Table 7-49. Read/Write Return to the Register Maps Table Figure 7-68. CTRL9 Control Register 7 6 5 4 3 2 1 0 EN_OL OL_MODE OL_T[1:0] STEP_EDGE RES_AUTO[1:0] EN_AUTO R/W-0b R/W-0b R/W-01b R/W-0b R/W-00b R/W-0b Table 7-49. CTRL9 Control Register Field Descriptions Bit Field Type Default Description 7 EN_OL R/W 0b Write 1b to enable open load detection. When this bit is 0b, open load detection is disabled. 6 OL_MODE R/W 0b 0b = nFAULT is released after latched OL fault is cleared using CLR_FLT bit or nSLEEP reset pulse 1b = nFAULT is released immediately after OL fault condition is removed 5-4 OL_T[1:0] R/W 01b Controls the open load fault detection time. • 00b = 30 ms (max) • 01b = 60 ms (max) • 10b = 120 ms (max) • 11b = Reserved 3 STEP_EDGE R/W 0b 0b = Active edge for STEP input is only rising edge 1b = Active edge for STEP input is both rising and falling edges DRV8461 SLOSE98 – DECEMBER 2022 www.ti.com 80 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8461 |
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