DRV8461SPWPR datasheet(5/117 Pages) TI

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TYPE

DESCRIPTION

NAME

DDW

PWP

SPI

Interface

H/W

Interface

RSVD/TOFF

Input

This pin is not used with SPI interface. With H/W interface, this

pin programs the OFF time for PWM current regulation.

VCP

Power

Charge pump output. Connect a X7R, 1-μF, 16-V ceramic

capacitor from VCP to VM.

2, 11, 12, 21

2, 13

Power

Power supply. Connect to motor supply voltage and bypass to

PGNDA and PGNDB with two 0.01-μF ceramic capacitors plus

a bulk capacitor rated for VM.

PGNDA

3, 10

Power

Power ground. Connect to system ground.

PGNDB

13, 20

Power

Power ground. Connect to system ground.

AOUT1

4, 5, 6

4, 5

Output

Winding A output. Connect to motor winding.

AOUT2

7, 8, 9

6, 7

Output

Winding A output. Connect to motor winding.

BOUT2

14, 15, 16

8, 9

Output

Winding B output. Connect to motor winding.

BOUT1

17, 18, 19

10, 11

Output

Winding B output. Connect to motor winding.

GND

22, 23

Power

Device ground. Connect to system ground.

DVDD

Power

Internal LDO output. Connect a X7R, 1-μF, 6.3-V or 10-V rated

ceramic capacitor to GND.

nFAULT

Open Drain

Fault indication output. Pulled logic low with fault condition.

Open-drain nFAULT requires an external pullup resistor.

nHOME

Open Drain

Pulled logic low when the internal indexer is at home position

(45°) of step table. The nHOME pin outputs one low pulse

per 360º electrical rotation (four fullsteps). Only available with

DDW package. See Section 7.3.5.1 for details.

MODE

Input

For the DDW package, MODE pin programs the device with

either SPI or hardware (H/W) pin interface. See Section 7.3.1

for details.

RSVD

29, 30, 31, 32

Reserved. Leave unconnected.

VREF

Input

Voltage reference input for setting full-scale current. DVDD

can be used to generate VREF through a resistor divider.

When configured with SPI interface, the VREF pin can be left

unconnected if VREF_INT_EN = 1b.

nSCS/M0

Input

With SPI interface, this pin acts as serial chip select. An active

low on this pin enables the serial interface communications.

With H/W interface, this pin programs the microstepping mode.

SDO/

DECAY1

Push-Pull/Input

With SPI interface, this pin acts as serial data output. Data

is shifted out on the rising edge of the SCLK pin. With H/W

interface, this pin programs the decay-mode.

SDI/DECAY0

Input

With SPI interface, this pin acts as serial data input. Data

is captured on the falling edge of the SCLK pin. With H/W

interface, this pin programs the decay-mode.

SCLK/M1

Input

With SPI interface, this pin acts as serial clock input. Serial

data is shifted out and captured on the corresponding rising

and falling edge on this pin. With H/W interface, this pin

programs the microstepping mode.

STEP

Input

Step input. An active edge causes the indexer to advance one

step. With SPI interface, STEP active edge can be either rising

edge or both rising and falling edge. With H/W interface, STEP

active edge is always the rising edge.

DIR

Input

Direction input. Logic level sets the direction of stepping.

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DRV8461

SLOSE98 – DECEMBER 2022

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