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DRV8461SPWPR 数据表(PDF) 67 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 67 Page - Texas Instruments |
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67 / 117 page  7.3.20.5 Functional Modes Summary Table 7-30. Functional Modes Summary CONDITION CONFIGURATION H-BRIDGE DVDD Regulator CHARGE PUMP INDEXER Logic Sleep mode 4.5 V < VM < 65 V nSLEEP pin = 0 Disabled Disbaled Disabled Disabled Disabled Operating 4.5 V < VM < 65 V nSLEEP pin = 1 ENABLE = 1 and EN_OUT = 1b Operating Operating Operating Operating Operating Disabled 4.5 V < VM < 65 V nSLEEP pin = 1 ENABLE pin = 0 or EN_OUT = 0b Disabled Operating Operating Operating Operating 7.4 Programming 7.4.1 Serial Peripheral Interface (SPI) Communication When configured to operate with SPI interface, the device has full duplex, 4-wire synchronous communication that is used to set device configurations, operating parameters, and read out diagnostic information from the device. This section describes the SPI protocol, the command structure, and the control and status registers. The SPI operates in target mode and can be connected with a controller in the following configurations: • One target device • Multiple target devices in parallel connection • Multiple target devices in series (daisy chain) connection 7.4.1.1 SPI Format The serial data input (SDI) word consists of a 16-bit word, with an 8 bit-command (A1), followed by 8-bit data (D1). The serial data output (SDO) word consists of 8 bits of status register with fault status indication (S1), followed by a report byte (R1). Figure 7-48 shows the data sequence between the controller and the SPI target driver. nSCS A1 D1 S1 R1 SDI SDO Figure 7-48. SPI Format - Standard "16-bit" Frame A valid frame must meet the following conditions: • The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high. • The nSCS pin should be taken high for at least 500 ns between frames. • When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is in the high-impedance state (Hi-Z). • A full 16 SCLK cycles must occur for a valid transaction for a standard frame, or alternately, for a daisy chainframe with "n" number of peripheral devices, 16 + (n x 16) SCLK cycles must occur for a valid transaction. Else, a frame error (SPI_ERROR) is reported and the data is ignored if it is a WRITE operation. • Data on SDO from the device is propagated on the rising edge of SCLK, while data on SDI is captured by thedevice on the subsequent falling edge of SCLK. • The most-significant bit (MSB) is shifted in and out first. www.ti.com DRV8461 SLOSE98 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: DRV8461 |
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