DRV8461SPWPR datasheet(10/117 Pages) TI

10 / 117 page

Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RDS(ONL)

Low-side FET on resistance

TJ = 25 °C, IO = 3 A

150

175

mΩ

TJ = 125 °C, IO = 3 A

225

285

mΩ

TJ = 150 °C, IO = 3 A

255

325

mΩ

ILEAK

Output leakage current to ground

in Disable mode(1)

H-bridges are Hi-Z, VVM = 65 V

200

μA

tRF

Output rise/fall time

H/W interface, IO = 3 A, between 10%

and 90%

140

SPI interface, SR = 0b, IO = 3 A,

between 10% and 90%

140

SPI interface, SR = 1b, IO = 3 A,

between 10% and 90%

Output dead time

VM = 24V, IO = 3 A

300

PWM CURRENT CONTROL (VREF)

Transimpedance gain

VREF = 3.3 V

1.045

1.1

1.164

V/A

IVREF

VREF Pin Leakage Current

VREF = 3.3 V

tOFF

PWM off-time

TOFF = 0 or TOFF = 00b

μs

TOFF = 1 or TOFF = 01b

TOFF = Hi-Z or TOFF = 10b

TOFF = 330kΩ to GND or TOFF = 11b

ΔITRIP_EXT

Current trip accuracy, external

VREF input

10% to 20% full-scale current

-10

20% to 40% full-scale current

-6

40% to 100% full-scale current

-5.5

5.5

ΔITRIP_INT

Current trip accuracy, internal

VREF

10% to 20% full-scale current

-10

20% to 40% full-scale current

-7

40% to 100% full-scale current

-6.5

6.5

IO,CH

AOUT and BOUT current

matching

100% full-scale current

-2.5

2.5

tBLK

Current regulation blanking time

SPI interface, TBLANK_TIME = 00b

μs

H/W interface or SPI interface,

TBLANK_TIME = 01b

1.5

SPI interface, TBLANK_TIME = 10b

SPI interface, TBLANK_TIME = 11b

2.5

tDEG

Current regulation deglitch time

0.5

μs

PROTECTION CIRCUITS

VMUVLO

VM UVLO lockout

VM falling

4.1

4.25

4.35

VM rising

4.2

4.35

4.46

VCCUVLO

VCC UVLO lockout

VCC connected to external voltage,

VCC falling

2.7

2.8

2.9

VCC connected to external voltage,

VCC rising

2.78

2.9

3.05

DRV8461

SLOSE98 – DECEMBER 2022

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