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DRV8461SPWPR 数据表(PDF) 72 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 72 Page - Texas Instruments |
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72 / 117 page  Table 7-33. Memory Map (continued) Register 7 6 5 4 3 2 1 0 Type Address CUSTOM_CTRL2 CUSTOM_CURRENT1[7:0] RW 0x17 CUSTOM_CTRL3 CUSTOM_CURRENT2[7:0] RW 0x18 CUSTOM_CTRL4 CUSTOM_CURRENT3[7:0] RW 0x19 CUSTOM_CTRL5 CUSTOM_CURRENT4[7:0] RW 0x1A CUSTOM_CTRL6 CUSTOM_CURRENT5[7:0] RW 0x1B CUSTOM_CTRL7 CUSTOM_CURRENT6[7:0] RW 0x1C CUSTOM_CTRL8 CUSTOM_CURRENT7[7:0] RW 0x1D CUSTOM_CTRL9 CUSTOM_CURRENT8[7:0] RW 0x1E ATQ_CTRL1 ATQ_CNT[7:0] R 0x1F ATQ_CTRL2 ATQ_CNT[10:8] RSVD ATQ_LRN_CONST1[10:8] RW 0x20 ATQ_CTRL3 ATQ_LRN_CONST1[7:0] RW 0x21 ATQ_CTRL4 ATQ_LRN_MIN_CURRENT[4:0] ATQ_LRN_CONST2[10:8] RW 0x22 ATQ_CTRL5 ATQ_LRN_CONST2[7:0] RW 0x23 ATQ_CTRL6 ATQ_UL[7:0] RW 0x24 ATQ_CTRL7 ATQ_LL[7:0] RW 0x25 ATQ_CTRL8 KP[7:0] RW 0x26 ATQ_CTRL9 RSVD KD[3:0] RW 0x27 ATQ_CTRL10 ATQ_EN LRN_START ATQ_FRZ[2:0] ATQ_AVG[2:0] RW 0x28 ATQ_CTRL11 ATQ_TRQ_MIN[7:0] RW 0x29 ATQ_CTRL12 ATQ_TRQ_MAX[7:0] RW 0x2A ATQ_CTRL13 ATQ_D_THR[7:0] RW 0x2B ATQ_CTRL14 RSVD RW 0x2C ATQ_CTRL15 ATQ_ERROR_TRUNCATE[3:0] ATQ_LRN_STEP[1:0] ATQ_LRN_CYCLE_SELECT[1:0] RW 0x2D ATQ_CTRL16 ATQ_TRQ_DAC[7:0] R 0x2E ATQ_CTRL17 RSVD VM_SCALE RSVD RW 0x2F ATQ_CTRL18 RSVD RW 0x30 SS_CTRL1 SS_SMPL_SEL[1:0] RSVD SS_PWM_FREQ[1:0] RSVD EN_SS RW 0x31 SS_CTRL2 SS_KP[7:0] RW 0x32 SS_CTRL3 SS_KI[7:0] RW 0x33 SS_CTRL4 RSVD SS_KI_DIV_SEL[2:0] RSVD SS_KP_DIV_SEL[2:0] RW 0x34 SS_CTRL5 SS_THR[7:0] RW 0x35 CTRL 14 VM_ADC[4:0] RSVD RW 0x3C Complex bit access types are encoded to fit into small table cells. Table 7-34 shows the codes that are used for access types in this section. Table 7-34. Access Type Codes Access Type Code Description Read Type R R Read Write Type DRV8461 SLOSE98 – DECEMBER 2022 www.ti.com 72 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8461 |
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