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DRV8461SPWPR 数据表(PDF) 56 Page - Texas Instruments

部件名 DRV8461SPWPR
功能描述  DRV8461: 65 V, 3 A Stepper Motor Driver for High Efficiency and Noiseless Operation
PDF  117 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRV8461SPWPR 数据表(HTML) 56 Page - Texas Instruments

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– FAULT bit becomes 0b
– UVLO bit stays at 0b
– nFAULT pin is pulled high.
VRST UVLO reset
or VCC UVLO
VUVLO rising
VUVLO falling
Device Status
SPI available
Digital Alive
Outputs switching
CP enabled
UVLO, FAULT bits 0b*
nFAULT high
Time
VM Voltage
SPI available
Digital Alive
Outputs Hi-Z
CP disabled
UVLO, FAULT bits 1b
nFAULT low
SPI unavailable
Digital Reset
Outputs Hi-Z
CP disabled
UVLO, FAULT bits 0b
nFAULT High
SPI available
Digital Alive
Outputs Hi-Z
CP disabled
UVLO bit 0b
FAULT bit 1b
nFAULT low
* FAULT bit will be 0b if no fault is present
SPI available
Digital Alive
Outputs switching
CP enabled
UVLO, FAULT bits 0b*
nFAULT high
Figure 7-40. Supply Voltage Ramp Profile
7.3.19.2 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the CPUV voltage:
• All the outputs are disabled (High-Z)
• nFAULT pin is driven low
• The charge pump remains active
• For the SPI version, the FAULT and CPUV bits are made 1b
Normal operation resumes (motor-driver operation and nFAULT released) when the VCP undervoltage condition
is removed. The CPUV bit remains at 1b until it is cleared through the CLR_FLT bit or an nSLEEP reset pulse.
7.3.19.3 Logic Supply Power on Reset (POR)
If at any time the voltage on the VCC pin falls below the VCCUVLO threshold:
• All the outputs are disabled (High-Z)
• Charge pump is disabled.
VCC UVLO is not reported on the nFAULT pin. Normal motor-driver operation resumes when the VCC
undervoltage condition is removed.
When device operates with SPI interface:
• The NPOR bit is reset and latched 0b once VCC goes above the UVLO threshold.
• NPOR remains in reset condition until cleared through the CLR_FLT bit or nSLEEP reset pulse.
• After power up, NPOR is automatically latched 1b once the CLR_FLT command is issued.
The VCC UVLO scenario is shown in Figure 7-41.
DRV8461
SLOSE98 – DECEMBER 2022
www.ti.com
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Product Folder Links: DRV8461



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