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DRV8461SPWPR 数据表(PDF) 96 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 96 Page - Texas Instruments |
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96 / 117 page  Figure 7-104. ATQ_CTRL17 Register (continued) R/W-0b R/W-0b R/W-000000b Table 7-88. ATQ_CTRL17 Register Field Descriptions Bit Field Type Default Description 7 RSVD R/W 0b Reserved. 6 VM_SCALE R/W 0b When this bit is 1b, the learning routine will automatically modify the values of the learning parameters in the event of a supply voltage change. 5-0 RSVD R/W 000000b Reserved. 7.5.5.18 ATQ_CTRL18 (address = 0x30) [Default = 00h] ATQ_CTRL18 is shown in Figure 7-105 and described in Table 7-89. Read/Write Return to the Register Maps Table Figure 7-105. ATQ_CTRL18 Register 7 6 5 4 3 2 1 0 RSVD R/W-00000000b Table 7-89. ATQ_CTRL18 Register Field Descriptions Bit Field Type Default Description 7-0 RSVD R/W 00000000b Reserved. 7.5.6 Silent Step Registers The silent step registers control the silent step decay mode. Silent step registers are read and write capable. Table 7-90 lists the memory-mapped registers for the silent step registers. All register offset addresses not listed in Table 7-90 should be considered as reserved locations and the register contents should not be modified. Table 7-90. Silent step Registers Summary Table Address Register Name Section 0x31 SS_CTRL1 Go 0x32 SS_CTRL2 Go 0x33 SS_CTRL3 Go 0x34 SS_CTRL4 Go 0x35 SS_CTRL5 Go 7.5.6.1 SS_CTRL1 (address = 0x31) [Default = 00h] SS_CTRL1 is shown in Figure 7-106 and described in Table 7-91. Read/Write Return to the Register Maps Table Figure 7-106. SS_CTRL1 Register 7 6 5 4 3 2 1 0 SS_SMPL_SEL[1:0] RSVD SS_PWM_FREQ[1:0] RSVD EN_SS R/W-00b R/W-00b R/W-00b R/W-0b R/W-0b DRV8461 SLOSE98 – DECEMBER 2022 www.ti.com 96 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8461 |
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