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DRV8461SPWPR 数据表(PDF) 4 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 4 Page - Texas Instruments |
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4 / 117 page  7 8 9 10 11 12 28 27 26 25 24 23 AOUT2 BOUT2 BOUT1 PGNDB VM nSLEEP ENABLE DIR STEP SCLK SDI Thermal PAD 1 2 3 4 5 6 CPL CPH VCP VM PGNDA AOUT1 22 21 20 19 18 17 SDO nSCS VREF nFAULT DVDD 13 14 AOUT1 AOUT2 BOUT2 16 15 GND BOUT1 VCC Figure 5-2. PWP Package (28-Pin HTSSOP) with SPI interface, Top View 7 8 9 10 11 12 28 27 26 25 24 23 AOUT2 BOUT2 BOUT1 PGNDB VM nSLEEP ENABLE DIR STEP M1 DECAY0 Thermal PAD 1 2 3 4 5 6 CPL CPH VCP VM PGNDA AOUT1 22 21 20 19 18 17 DECAY1 M0 VREF nFAULT DVDD 13 14 AOUT1 AOUT2 BOUT2 16 15 GND BOUT1 TOFF Figure 5-3. PWP Package (28-Pin HTSSOP) with H/W interface, Top View PIN TYPE DESCRIPTION NAME DDW PWP SPI Interface H/W Interface VCC 25 19 - Power Supply voltage for internal logic blocks. When separate logic supply voltage is not available, tie the VCC pin to the DVDD pin. When configured with SPI interface, the VCC pin also acts as the supply pin for SDO output. See Section 7.3.16 for details. DRV8461 SLOSE98 – DECEMBER 2022 www.ti.com 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8461 |
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