| 数据搜索系统,热门电子元器件搜索 |
|
DRV8461SPWPR 数据表(PDF) 53 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DRV8461SPWPR 数据表(HTML) 53 Page - Texas Instruments |
|
53 / 117 page ![]() Figure 7-33. Quad-Level Input Pin Diagram Figure 7-34 shows the input structure for STEP, DIR, MODE, SDI, SCLK, DECAY1 and nSLEEP pins. Figure 7-34. Logic-Level Input Pin Diagram The following diagram shows the input structure for the logic-level pin nSCS. Figure 7-35. nSCS Input Pin Diagram 7.3.18 Spread Spectrum Spread spectrum or frequency dithering is used to reduce the effect of EMI by converting a narrowband signal into a wideband signal, which will spread the energy across multiple frequencies. Figure 7-36 illustrates how manipulating the clock frequency over time has the effect of spreading the energy. In the context of the DRV8461, the frequencies of the internal clock for digital circuits (10 MHz typical) and the clock for charge pump (357 kHz typical) are manipulated to reduce the peak energy and is distributed to other frequencies and their harmonics. This feature combined with output slew rate control minimizes the radiated emissions from the device and helps pass strict EMI standards. www.ti.com DRV8461 SLOSE98 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: DRV8461 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |