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DRV8461SPWPR 数据表(PDF) 82 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 82 Page - Texas Instruments |
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82 / 117 page  Table 7-51. CTRL11 Control Register Field Descriptions Bit Field Type Default Description 7-0 TRQ_DAC[7:0] R/W 11111111b Determines the run current. • 11111111b = 256/256 x 100% • 11111110b = 255/256 x 100% • 11111101b = 254/256 x 100% • 11111100b = 253/256 x 100% • .................... • 00000000b = 1/256 x 100% 7.5.2.12 CTRL12 (address = 0x0F) [Default = 20h] CTRL12 is shown in Figure 7-71 and described in Table 7-52. Read/Write Return to the Register Maps Table Figure 7-71. CTRL12 Control Register 7 6 5 4 3 2 1 0 EN_STSL TSTSL_FALL[3:0] RSVD R/W-0b R/W-0100b R/W-000b Table 7-52. CTRL12 Control Register Field Descriptions Bit Field Type Default Description 7 EN_STSL R/W 0b 0b = Standstill power saving mode disabled 1b = Standstill power saving mode enabled 6-3 TSTSL_FALL[3:0] R/W 0100b Controls the time it takes the current to reduce from TRQ_DAC to ISTSL after TSTSL_DLY time has elapsed • 0000b: fall time = 0 • 0001b: fall time for each current step = 1 ms • ............ • 0100b: fall time for each current step = 4 ms • ............ • 1111b: fall time for each current step = 15 ms 2-0 RSVD R/W 000b Reserved 7.5.2.13 CTRL13 (address = 0x10) [Default = 10h] CTRL13 is shown in Figure 7-72 and described in Table 7-53. Read/Write Return to the Register Maps Table Figure 7-72. CTRL13 Control Register 7 6 5 4 3 2 1 0 TSTSL_DLY[5:0] VREF_INT_EN RSVD R/W-000100b R/W-0b R/W-0b DRV8461 SLOSE98 – DECEMBER 2022 www.ti.com 82 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8461 |
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