DRV8461SPWPR datasheet(64/117 Pages) TI

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7.3.19.7 Overtemperature Warning (OTW)

Overtemperature warning is detected if the die temperature exceeds the trip point of the overtemperature

warning (TOTW). This feature is supported only if the device is operating with SPI interface.

When the OTW is detected -

• OTW and TF bits are made 1b

• The device performs no additional action and continues to function.

• The charge pump remains active.

• If the TW_REP bit is 1b -

– nFAULT is pulled low in the event of OTW

– FAULT bit is made 1b

When the die temperature falls below the hysteresis point (THYS_OTW) of the overtemperature warning, the OTW

and TF bits clear automatically.

7.3.19.8 Thermal Shutdown (OTSD)

Thermal shutdown is detected if the die temperature exceeds the thermal shutdown limit (TOTSD). When thermal

shutdown is detected -

• All MOSFETs in the H-bridges are disabled

• nFAULT is driven low

• Charge pump is disabled

• For operation with SPI interface

– FAULT, TF and OTS bits are set to 1b

The recovery from thermal shutdown protection can be in two different modes: latched shutdown and automatic

retry. The recovery modes can be changed on the fly.

7.3.19.8.1 Latched Shutdown

To select latched shutdown mode,

• If device is operating with H/W interface, the ENABLE pin should be Hi-Z

• If device is operating with SPI interface, OTSD_MODE should be 0b

In this mode, after the junction temperature falls below the overtemperature threshold limit minus the hysteresis

(TOTSD – THYS_OTSD), normal operation resumes after applying an nSLEEP reset pulse or a power cycling.

7.3.19.8.2 Automatic Retry

To select automatic retry mode,

• For H/W interface, the ENABLE pin has to be logic HIGH (>2.7V)

• For SPI interface, OTSD_MODE bit should be 1b

In this mode, normal operation resumes (motor-driver operation and the nFAULT line released) when the

junction temperature falls below the overtemperature threshold limit minus the hysteresis (TOTSD – THYS_OTSD).

When operating with SPI interface, the TF and OTS bits remain latched to 1b indicating that a thermal event

occurred until a clear faults command is issued either via the CLR_FLT bit or an nSLEEP reset pulse.

7.3.19.9 Supply voltage sensing

An internal ADC monitors the supply voltage applied to the motor driver and outputs the value on the VM_ADC

bits in the CTRL14 register. The default value is 01011b, corresponding to 24 V.

This supply voltage reading can be used to implement overvoltage protection by the controller, by disabling the

motor driver when the supply voltage exceeds a predetermined threshold.

7.3.19.10 nFAULT Output

The nFAULT pin has an open-drain output and should be pulled up to a 5-V, 3.3-V or 1.8-V supply. nFAULT pin

will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. For a 5-V pullup, the

DRV8461

SLOSE98 – DECEMBER 2022

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