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DRV8461SPWPR 数据表(PDF) 57 Page - Texas Instruments

部件名 DRV8461SPWPR
功能描述  DRV8461: 65 V, 3 A Stepper Motor Driver for High Efficiency and Noiseless Operation
PDF  117 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRV8461SPWPR 数据表(HTML) 57 Page - Texas Instruments

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4.5V
65V
nSLEEP
VCC
UVLO
H-BRIDGE,
CHARGE PUMP,
DIGITAL
ENABLED
DISABLED
DVDD
nFAULT
+V
NPOR
CLR_FLT
Figure 7-41. Logic Supply POR
7.3.19.4 Overcurrent Protection (OCP)
An analog current-limit circuit on any MOSFET limits the current through that MOSFET by removing the gate
drive. If this current limit persists for longer than the tOCP time, an overcurrent fault is detected.
• The MOSFETs in both H-bridges are disabled
• nFAULT is driven low
• Charge pump remains active.
• When operating with SPI interface -
– FAULT and OCP bits are latched 1b
– For xOUTy to VM short, corresponding OCP_LSy_x bit becomes 1b
– For xOUTy to ground short, corresponding OCP_HSxy_x bit becomes 1b
– The TOCP bit programs the overcurrent protection deglitch time.
The overcurrent protection can operate in two different modes: latched shutdown and automatic retry. The
operating modes can be changed on the fly.
7.3.19.4.1 Latched Shutdown
To select latched shutdown mode:
• For H/W interface, the ENABLE pin has to be Hi-Z
• For SPI interface, the OCP_MODE bit should be 0b
In this mode, once the OCP condition is removed, normal operation resumes after applying a CLR_FLT
command, an nSLEEP reset pulse or a power cycling.
7.3.19.4.2 Automatic Retry
To select automatic retry mode:
• For H/W interface, the ENABLE pin has to be HIGH (> 2.7 V)
• For SPI interface, the OCP_MODE bit should be 1b
In this mode, normal operation resumes automatically (motor-driver operation and nFAULT released) after the
tRETRY time has elapsed and the fault condition is removed.
www.ti.com
DRV8461
SLOSE98 – DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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